The field of the invention is that of forming DRAM cells having high aspect ratio trenches in integrated circuit processing.
As ground rule dimensions shrink in integrated circuits, the problem of filling high aspect ratio trenches increases, in particular for trench capacitors used in DRAM cells that are commonly used in advanced processing.
The industry-standard filling process has been photoresist, applied and stripped several times. This method has been widely adopted because photoresist is well understood.
Since resist cannot stand the high temperatures used in front end processing, it is necessary to strip the resist and refill the trench when a step is to be performed at a temperature greater than 300 C. This occurs more than once in the course of the deep trench processing module.
As an additional consideration, the lengthy processes required to fabricate an integrated circuit are currently highly integrated; i.e. a change in a single process step can affect the result of steps performed before and after it, sometimes affecting steps that are not immediately before or after, but separated in time by several other steps.
It is therefore a multi-dimensional or multi-factor decision to change a process step. It is not enough that the new step produce a tougher, or thinner, or lower-density film, or take less time to put down. It is also required that the new step not produce disadvantages in other aspects of the process that outweigh the benefits.
The steps in a typical prior art method up to forming the buried plate of the trench capacitor are a) etching a deep trench in a silicon substrate; b) forming a barrier layer on a trench sidewall; c) filling the trench with photoresist; d) recessing (etching) the photoresist to a pre-determined depth, so a top part of deep trench is exposed; e) removing the barrier layer in the upper region to expose the trench sidewall; f) stripping the photoresist; g) forming a collar on the side wall upper portion using the barrier layer as a mask in the lower portion; and h) forming a buried plate diffusion region in the trench lower region using the collar as a mask for the upper portion.
The main function of the barrier material in the prior art method is to protect the lower portion of the trench during the steps of forming the collar.
The barrier material is typically nitride or a composite of oxide and nitride.
This is a fairly complicated and expensive process and it would be highly desirable to have a process with fewer and/or less expensive steps that produced an equivalent result.
In a particular prior art example, shown in U.S. Pat. No. 6,271,142, the method uses a partial fill scheme of deep trenches with spin-on material that is immediately followed by a collar formation. Partial fill of deep trenches has a very high non-uniformity of SOG (the reference point is thickness of SOG material at deep trench bottom—thousands of Angstroms). This approach can not be implemented in manufacturing. Partial fill requires an ideal structure with all Deep Trenches being of identical size since SOG thickness is proportional to trench volume. This method can not fill trenches of different sizes and volumes, which is typical for any real DRAM device. The patent also does not address the problem of final removal of SOG from the wafer surface, since it does not use any etch or CMP techniques.
SOG has a tendency to outgas and/or to crack or delaminate as a result of thermal stress. The probability of cracking is dependent on the thickness of the layer and also on the density of the pattern and topology. Those skilled in the art have been reluctant to use SOG as a trench filler because of the cracking problem and the difficulty of predicting what thickness is safe to use.